View PCF2123U12AA_3726785.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the pcf2123 is a cmos 1 real-time clock (rtc) and calendar optimized for low power applications. data is transferred serially via a serial peripheral interface (spi-bus) with a maximum data rate of 6.25 mbit/s. an alarm and timer function is also available providing the possibility to generate a wake-up signal on an interrupt pin. an offset register allows ?ne tuning of the clock. 2. features n real time clock provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 khz quartz crystal n low backup current while running: typical 100 na at v dd = 2.0 v and t amb =25 c n resolution: seconds to years n watchdog functionality n freely programmable timer and alarm with interrupt capability n clock operating voltage: 1.1 v to 5.5 v n 3 line spi-bus with separate, but combinable data input and output n serial interface at v dd = 1.6 v to 5.5 v n 1 second or 1 minute interrupt output n integrated oscillator load capacitors for c l =7pf n internal power-on reset (por) n open-drain interrupt and clock output pins n programmable offset register for frequency adjustment 3. applications n time keeping application n battery powered devices n metering n high duration timers n daily alarms n low standby power applications pcf2123 spi real time clock/calendar rev. 02 4 december 2009 product data sheet 1. the de?nition of the abbreviations and acronyms used in this data sheet can be found in section 19 .
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 2 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 4. ordering information [1] sawn wafer on film frame carrier (ffc). [2] sawn wafer with gold bumps on film frame carrier (ffc). 5. marking table 1. ordering information type number package name description version pcf2123ts tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 pcf2123bs hvqfn16 plastic thermal enhanced very thin quad ?at package; no leads; 16 terminals; body 3 3 0.85 mm sot758-1 pcf2123u/10aa pcf2123u/10 wire bond die; 12 bonding pads; 1.492 1.449 0.20 mm [1] pcf2123u/10 pcf2123u/12aa pcf2123u/12 wlcsp12; wafer level chip size package; 12 bumps; 1.492 1.449 0.22 mm [2] pcf2123u/12 table 2. marking codes type number marking code pcf2123ts pcf2123 pcf2123bs 123 pcf2123u/10aa pc2123-1 pcf2123u/12aa pc2123-1
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 3 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 6. block diagram fig 1. block diagram of pcf2123 013aaa223 pcf2123 oscillator 32.768 khz divider clock out interrupt clkout clkoe int offset function offset_register 0dh monitor power on reset watch dog spi interface osci ce scl sdi sdo osco v dd test v ss timer function timer_clkout 0eh countdown_timer 0fh control control_1 00h control_2 01h time seconds 02h minutes 03h hours 04h days 05h alarm function minute_alarm 09h hour_alarm 0ah day_alarm 0bh weekday_alarm 0ch weekdays 06h months 07h years 08h c osci c osco r pd
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 4 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 7. pinning information 7.1 pinning top view. for mechanical details, see figure 30 . for mechanical details, see figure 31 . fig 2. pin con?guration for tssop14 (pcf2123ts) fig 3. pin con?guration for hvqfn16 (pcf2123bs) pcf2123 osci v dd osco clkout n.c. clkoe test n.c. int scl ce sdi v ss sdo 001aai551 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aai550 pcf2123 transparent top view ce sdi int scl test clkoe osco clkout v ss n.c. n.c. sdo osci n.c. n.c. v dd 4 9 3 10 2 11 1 12 5 6 7 8 16 15 14 13 terminal 1 index area viewed from active side. for mechanical details, see figure 32 and figure 33 . fig 4. pin con?guration for pcf2123u/10 (bare die) and pcf2123u/12 (bare die) 001aai544 7 6 osci v dd pcf2123u 8 osco 9 test 10 int 11 ce 12 v ss 5 clkout 4 clkoe 3 scl 2 sdi 1 sdo
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 5 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 7.2 pin description [1] the die paddle (exposed pad) is wired to v ss but should not be electrically contacted. [2] the substrate (rear side of the die) is wired to v ss but should not be electrically contacted. 8. device protection diagram table 3. pin description symbol pin description tssop14 hvqfn16 pcf2123ux osci 1 16 7 oscillator input; high-impedance node; minimize wire length between quartz and package osco 2 1 8 oscillator output; high-impedance node; minimize wire length between quartz and package n.c. 3, 11 6, 7, 14, 15 - do not connect and do not use as feed through; connect to v dd if ?oating pins are not allowed test 4 2 9 test pin; not user accessible; connect to v ss or leave ?oating (internally pulled down) int 5 3 10 interrupt output (open-drain; active low) ce 6 4 11 chip enable input (active high) with internal pull down v ss 75 [1] 12 [2] ground sdo 8 8 1 serial data output, push-pull; high-impedance when not driving; can be connected to sdi for single wire data line sdi 9 9 2 serial data input; may ?oat when ce is inactive scl 10 10 3 serial clock input; may ?oat when ce is inactive clkoe 12 11 4 clkout enable or disable pin; enable is active high clkout 13 12 5 clock output (open-drain) v dd 14 13 6 supply voltage; positive or negative steps in v dd may affect oscillator performance; recommend 100 nf decoupling close to device (see figure 29 ) fig 5. device diode protection diagram of pcf2123 001aai552 sdo sdi scl clkout clkoe v dd osci osco test int ce v ss pcf2123
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 6 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9. functional description the pcf2123 contains 16 8-bit registers with an auto-incrementing address counter, an on-chip 32.768 khz oscillator with two integrated load capacitors, a frequency divider which provides the source clock for the real time clock (rtc), a programmable clock output, and a 6.25 mbit/s spi-bus. an offset register allows ?ne tuning of the clock. all 16 registers are designed as addressable 8-bit parallel registers although not all bits are implemented. ? the ?rst two registers (memory address 00h and 01h) are used as control registers. ? the memory addresses 02h through 08h are used as counters for the clock function (seconds up to years). the registers seconds, minutes, hours, days, weekdays, months, and years are all coded in binary coded decimal (bcd) format. when one of the rtc registers is read the contents of all counters are frozen. therefore, faulty reading of the clock and calendar during a carry condition is prevented. ? addresses 09h through 0ch de?ne the alarm condition. ? address 0dh de?nes the offset calibration. ? address 0eh de?nes the clock out and timer mode. ? address registers 0eh and 0fh are used for the countdown timer function. the countdown timer has four selectable source clocks allowing for countdown periods in the range from 244 m s up to four hours. there are also two pre-de?ned timers which can be used to generate an interrupt once per second or once per minute. these are de?ned in register control_2 (01h). 9.1 low power operation minimum power operation will be achieved by reducing the number and frequency of switching signals inside the ic, i.e., low frequency timer clocks and a low frequency clkout will result in lower operating power. a second prime consideration is the series resistance r s of the quartz used. 9.1.1 power consumption with respect to quartz series resistance the series resistance acts as a loss element. low r s will reduce current consumption further.
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 7 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.1.2 power consumptions with respect to timer mode four source clocks are possible for the timer. the 4.096 khz source clock will add the greatest part to the power consumption. the selection of 64 hz, 1 hz or 1 60 hz will be almost indistinguishable and add very little. con?guration: clkout disabled, v dd = 3 v, timer clock set to 1 60 hz. (1) i dd (na) minimum power mode. (2) maximum value for r s is 100 k w . fig 6. i dd with respect to quartz r s rs (2) (k w ) 0 100 80 40 60 20 001aai558 130 170 90 210 250 i dd (1) (na) 50 con?guration: clkout disabled, quartz r s =15k w . (1) i dd (na) minimum power mode. (2) timer clock = 4 khz. (3) timer clock = 64 hz, 1 hz, 1 60 hz. fig 7. i dd with respect to timer clock selection v dd (v) 0 6 4 2 001aai559 200 100 300 400 i dd (1) (na) 0 (2) (3)
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 8 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.2 register overview 16 registers are available. the time registers are encoded in the binary coded decimal (bcd) format to simplify application use. other registers are either bit-wise or standard binary. [1] except in the case of software reset, see section 9.5 . table 4. registers overview bit positions labelled as - are not implemented and will return a 0 when read. bit positions labelled with n should always be written with logic 0 [1] . address register name bit 7 6 5 4 3 2 1 0 control and status registers 00h control_1 ext_test n stop sr n 12_24 cie n 01h control_2 mi si msf ti_tp af tf aie tie time and date registers 02h seconds os seconds (0 to 59) 03h minutes - minutes (0 to 59) 04h hours - - ampm hours (1 to 12) in 12 h mode hours (0 to 23) in 24 h mode 05h days - - days (1 to 31) 06h weekdays - - - - - weekdays (0 to 6) 07h months - - - months (1 to 12) 08h years years (0 to 99) alarm registers 09h minute_alarm ae_m minute_alarm (0 to 59) 0ah hour_alarm ae_h - ampm hour_alarm (1 to 12) in 12 h mode hour_alarm (0 to 23) in 24 h mode 0bh day_alarm ae_d - day_alarm (1 to 31) 0ch weekday_alarm ae_w - - - - weekday_alarm (0 to 6) offset register 0dh offset_register mode offset[6:0] timer registers 0eh timer_clkout - cof[2:0] te - ctd[1:0] 0fh countdown_timer countdown_timer[7:0]
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 9 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.3 control registers 9.3.1 register control_1 [1] default value. [2] for a software reset, 01011000 (58h) must be sent to register control_1 (see section 9.5 ). table 5. control_1 - control and status register 1 (address 00h) bit description bit symbol value description reference 7 ext_test 0 [1] normal mode section 9.12 1 external clock test mode 6 n - unused - 5stop 0 [1] the rtc source clock runs section 9.13 1 the rtc clock is stopped; rtc divider chain ?ip-?ops are asynchronously set to logic 0; clkout at 32.768 khz, 16.384 khz or 8.192 khz is still available 4sr 0 [1] no software reset section 9.5 1 initiate software reset [2] ; this register will always return a 0 when read 3 n - unused - 2 12_24 0 [1] 24 hour mode is selected - 1 12 hour mode is selected 1 cie 0 [1] no correction interrupt generated section 9.11 1 interrupt pulses will be generated at every correction cycle 0 n - unused -
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 10 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.3.2 register control_2 [1] default value. 9.4 os ?ag the pcf2123 includes a ?ag (os in register seconds, see t ab le 8 ) which is set whenever the oscillator is stopped (see figure 8 and figure 9 ). the ?ag will remain set until cleared by software. if the ?ag cannot be cleared, then the pcf2123 oscillator is not running. this method can be used to monitor the oscillator and to determine if the supply voltage has reduced to the point where oscillation fails. table 6. control_2 - control and status register 2 (address 01h) bits description bit symbol value description reference 7mi 0 [1] minute interrupt is disabled section 9.8.3 1 minute interrupt is enabled 6si 0 [1] second interrupt is disabled 1 second interrupt is enabled 5 msf 0 [1] no minute or second interrupt generated 1 ?ag set when minute or second interrupt generated; ?ag must be cleared to clear interrupt when ti_ip = 0 4 ti_tp 0 [1] interrupt pin follows timer ?ags section 9.9.2 1 interrupt pin generates a pulse 3af 0 [1] no alarm interrupt generated section 9.7.5 1 ?ag set when alarm triggered; ?ag must be cleared to clear interrupt 2tf 0 [1] no countdown timer interrupt generated section 9.8.4 1 ?ag set when countdown timer interrupt generated; ?ag must be cleared to clear interrupt when ti_ip = 0 1 aie 0 [1] no interrupt generated from the alarm ?ag section 9.9.3 1 interrupt generated when alarm ?ag set 0 tie 0 [1] no interrupt generated from the countdown timer section 9.9.2 1 interrupt generated by the countdown timer
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 11 of 55 nxp semiconductors pcf2123 spi real time clock/calendar the oscillator may be stopped, for example, by grounding one of the oscillator pins, osci or osco. the oscillator is also considered to be stopped during the time between power-on and stable crystal resonance. this time may be in the range of 200 ms to 2 s depending on crystal type, temperature and supply voltage. at power-on the os ?ag is always set. 9.5 reset a reset is automatically generated at power-on. a reset can also be initiated with the software reset command. it is generally recommended to make a software reset after power-on. a software reset can be initiated by setting the bits 6, 4 and 3 in register control_1 logic 1 and all other bits logic 0 by sending the bit sequence 01011000 (58h), see figure 10 . if this bit sequence is not correct, the software reset instruction will be ignored to protect the device from accidently being reset. when sending the software instruction, the other bits are not written. fig 8. os set by failing v dd fig 9. os ?ag 001aai561 v dd v osc(min) t battery operation main supply 001aai553 os = 1 and flag can not be cleared os = 1 and flag can be cleared os flag cleared by software os flag set when oscillation stops oscillation now stable t v dd oscillation os flag
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 12 of 55 nxp semiconductors pcf2123 spi real time clock/calendar after reset, the following mode is entered: ? 32.768 khz on pin clkout active ? 24 hour mode is selected ? offset register is set to 0 ? no alarms set ? timer disabled ? no interrupts enabled (1) when ce is inactive, the interface is reset. fig 10. software reset command table 7. register reset values bits labeled as - are not implemented. bits labeled as x are unde?ned at power-on and unchanged by subsequent resets. address register name bit 7 6 5 4 3 2 1 0 00h control_1 0 0 0 0 0 0 0 0 01h control_2 0 0 0 0 0 0 0 0 02h seconds 1 x x x x x x x 03h minutes - x x x x x x x 04h hours - - x x x x x x 05h days - - x x x x x x 06h weekdays - - - - - x x x 07h months - - - x x x x x 08h years x x x x x x x x 09h minute_alarm 1 x x x x x x x 0ah hour_alarm 1 - x x x x x x 0bh day_alarm 1 - x x x x x x 0ch weekday_alarm 1 - - - - x x x 0dh offset_register 0 0 0 0 0 0 0 0 0eh timer_clkout - 0 0 0 0 - 1 1 0fh countdown_timer x x x x x x x x 001aai562 addr 00 hex software reset 58 hex r/w b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 b7 0 b6 1 b5 0 b4 1 b3 1 b2 0 b1 0 b0 0 internal reset signal ce scl (1)
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 13 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.6 time and date function the majority of the registers are coded in the binary coded decimal (bcd) format. bcd is used to simplify application use. an example is shown for the seconds in t ab le 9 . 9.6.1 register seconds [1] default value. 9.6.2 register minutes 9.6.3 register hours table 8. seconds - seconds register (address 02h) bit description bit symbol value place value description 7 os 0 - clock integrity is guaranteed 1 [1] - clock integrity is not guaranteed; oscillator has stopped or been interrupted 6 to 4 seconds 0 to 5 tens place actual seconds coded in bcd format, see t ab le 9 3 to 0 0 to 9 unit place table 9. seconds coded in bcd format seconds value (decimal) upper-digit (tens place) digit (unit place) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 00000000 01 00000001 02 00000010 : :::::::: 09 00001001 10 00010000 : :::::::: 58 01011000 59 01011001 table 10. minutes - minutes register (address 03h) bit description bit symbol value place value description 7 - - - unused 6 to 4 minutes 0 to 5 tens place actual minutes coded in bcd format 3 to 0 0 to 9 unit place table 11. hours - hours register (address 04h) bit description bit symbol value place value description 7 to 6 - - unused 12 hour mode [1] 5 ampm 0 - indicates am 1 - indicates pm 4 hours 0 to 1 tens place actual hours in 12 hour mode coded in bcd format 3 to 0 0 to 9 unit place
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 14 of 55 nxp semiconductors pcf2123 spi real time clock/calendar [1] hour mode is set by the 12_24 bit in register control_1. 9.6.4 register days [1] the pcf2123 compensates for leap years by adding a 29th day to february if the year counter contains a value which is exactly divisible by 4, including the year 00. 9.6.5 register weekdays [1] de?nition may be re-assigned by the user. 9.6.6 register months 24 hour mode [1] 5 to 4 hours 0 to 2 tens place actual hours in 24 hour mode coded in bcd format 3 to 0 0 to 9 unit place table 11. hours - hours register (address 04h) bit description continued bit symbol value place value description table 12. days - days register (address 05h) bit description bit symbol value place value description 7 to 6 - - - unused 5to4 days [1] 0 to 3 tens place actual day coded in bcd format 3 to 0 0 to 9 unit place table 13. weekdays - weekdays register (address 06h) bit description bit symbol value description 7 to 3 - - unused 2 to 0 weekdays 0 to 6 actual weekday values, see t ab le 14 table 14. weekday assignments day [1] bit 2 1 0 sunday 0 0 0 monday 0 0 1 tuesday 0 1 0 wednesday 0 1 1 thursday 1 0 0 friday 1 0 1 saturday 1 1 0 table 15. months - months register (address 07h) bit description bit symbol value place value description 7 to 5 - - - unused 4 months 0 to 1 tens place actual month coded in bcd format, see t ab le 16 3 to 0 0 to 9 unit place
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 15 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.6.7 register years 9.6.8 setting and reading the time figure 11 shows the data ?ow and data dependencies starting from the 1 hz clock tick. table 16. month assignments in bcd format month upper-digit (tens place) digit (unit place) bit 4 bit 3 bit 2 bit 1 bit 0 january 0 0 0 0 1 february 0 0 0 1 0 march 0 0 0 1 1 april 0 0 1 0 0 may00101 june00110 july00111 august 0 1 0 0 0 september 0 1 0 0 1 october 1 0 0 0 0 november 1 0 0 0 1 december 1 0 0 1 0 table 17. years - years register (08h) bit description bit symbol value place value description 7 to 4 years 0 to 9 tens place actual year coded in bcd format 3 to 0 0 to 9 unit place fig 11. data ?ow of the time function 001aaf901 1 hz tick 12_24 hour mode weekday seconds minutes hours days leap year calculation months years
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 16 of 55 nxp semiconductors pcf2123 spi real time clock/calendar during read/write operations, the time counting circuits (memory locations 02h through 08h) are blocked. this prevents ? faulty reading of the clock and calendar during a carry condition ? incrementing the time registers during the read cycle after this read/write access is completed, the time circuit is released again and any pending request to increment the time counters that occurred during the read/write access is serviced. a maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see figure 12 ). as a consequence of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. failing to comply with this method could result in the time becoming corrupted. as an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time may increment between the two accesses. a similar problem exists when reading. a roll over may occur between reads thus giving the minutes from one moment and the hours from the next. therefore it is advised to read all time and date registers in one access. 9.7 alarm function when one or more of these registers are loaded with a valid minute, hour, day, or weekday and its corresponding alarm enable bit (ae_x) is logic 0, then that information will be compared with the current minute, hour, day, and weekday. 9.7.1 register minute_alarm [1] default value. fig 12. access time for read/write operations t < 1 s 013aaa222 command data bus chip enable data data data table 18. minute_alarm - minute alarm register (address 09h) bit description bit symbol value place value description 7 ae_m 0 - minute alarm is enabled 1 [1] - minute alarm is disabled 6 to 4 minute_alarm 0 to 5 tens place minute alarm information coded in bcd format 3 to 0 0 to 9 unit place
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 17 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.7.2 register hour_alarm [1] default value. [2] hour mode is set by the 12_24 bit in register control_1. 9.7.3 register day_alarm [1] default value. 9.7.4 register weekday_alarm [1] default value. 9.7.5 alarm ?ag by clearing the msb, ae_x (alarm enable), of one or more of the alarm registers the corresponding alarm condition(s) are active. when an alarm occurs, af (register control_2, see t ab le 6 ) is set logic 1. the asserted af can be used to generate an interrupt ( int). the af is cleared using the interface. table 19. hour_alarm - hour alarm register (address 0ah) bit description bit symbol value place value description 7 ae_h 0 hour alarm is enabled 1 [1] hour alarm is disabled 6 - - unused 12 hour mode [2] 5 ampm 0 indicates am 1 indicates pm 4 hour_alarm 0 to 1 tens place hour alarm information coded in bcd format when in 12 hour mode 3 to 0 0 to 9 unit place 24 hour mode [2] 5 to 4 hour_alarm 0 to 2 tens place hour alarm information coded in bcd format when in 24 hour mode 3 to 0 0 to 9 unit place table 20. day_alarm - day alarm register (address 0bh) bit description bit symbol value place value description 7 ae_d 0 - day alarm is enabled 1 [1] - day alarm is disabled 6 - - - unused 5 to 4 day_alarm 0 to 3 tens place day alarm information coded in bcd format 3 to 0 0 to 9 unit place table 21. weekday_alarm - weekday alarm register (address 0ch) bit description bit symbol value description 7 ae_w 0 weekday alarm is enabled 1 [1] weekday alarm is disabled 6 to 3 - - unused 2 to 0 weekday_alarm 0 to 6 weekday alarm information coded in bcd format
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 18 of 55 nxp semiconductors pcf2123 spi real time clock/calendar the registers at addresses 09h through 0ch contain alarm information. when one or more of these registers is loaded with minute, hour, day, or weekday, and its corresponding alarm enable bit (ae_x) is logic 0, then that information is compared with the current minute, hour, day, and weekday. when all enabled comparisons ?rst match, the alarm flag (af) is set logic 1. the generation of interrupts from the alarm function is controlled via bit aie (register control_2, see t ab le 6 ). if bit aie is enabled, the int pin follows the condition of bit af. af will remain set until cleared by the interface. once af has been cleared, it will only be set again when the time increments to match the alarm condition once more. alarm registers which have their ae_x bit logic 1 are ignored. generation of interrupts from the alarm function is described in section 9.9.3 . (1) only when all enabled alarm settings are matching. its only on increment to a matched case that the alarm ?ag is set, see section 9.7.5 . fig 13. alarm function block diagram example where only the minute alarm is used and no other interrupts are enabled. fig 14. alarm ?ag timing 013aaa088 weekday alarm ae_w weekday time = day alarm ae_d day time = hour alarm ae_h hour time = minute alarm ae_m minute time = check now signal set alarm flag af (1) ae_m = 1 1 0 example 001aaf903 44 45 45 minute alarm minutes counter af int when aie = 1 46
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 19 of 55 nxp semiconductors pcf2123 spi real time clock/calendar figure 14 , t ab le 22 and t ab le 23 show an example for clearing bit af, but leaving bit msf and bit tf unaffected. the ?ags are cleared by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. repeatedly re-writing these bits has no in?uence on the functional behavior. to prevent the timer ?ags being overwritten while clearing bit af, logic and is performed during a write access. a ?ag is cleared by writing logic 0 whilst a ?ag is not cleared by writing logic 1. writing logic 1 will result in the ?ag value remaining unchanged. t ab le 23 shows what instruction must be sent to clear bit af. in this example, bit msf and bit tf are unaffected. 9.8 timer functions the countdown timer has four selectable source clocks allowing for countdown periods in the range from 244 m s to 4 h 15 min. there are also two pre-de?ned timers which can be used to generate an interrupt once per second or once per minute. for periods greater than 4 hours, the alarm function can be used. registers 01h, 0eh and 0fh are used to control the timer function and output. 9.8.1 register timer_clkout [1] values of cof[2:0] see t ab le 35 . [2] default value. table 22. flag location in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 - - msf - af tf - - table 23. example to clear only af (bit 3) in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 - - 1 - 0 1 - - table 24. timer_clkout - timer control register (address 0eh) bit description bit symbol value description reference 7 - - unused - 6 to 4 cof[2:0] [1] clkout control section 9.10 3 te 0 countdown timer is disabled section 9.8.4 1 countdown timer is enabled 2 - - unused 1 to 0 ctd[1:0] 00 4.096 khz countdown timer source clock 01 64 hz countdown timer source clock 10 1 hz countdown timer source clock 11 [2] 1 60 hz countdown timer source clock
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 20 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.8.2 register countdown_timer 9.8.3 minute and second interrupt the minute and second interrupts (bits mi and si) are pre-de?ned timers for generating periodic interrupts. the timers can be enabled independently from one another. however, a minute interrupt enabled on top of a second interrupt will not be distinguishable since it will occur at the same time; see figure 15 . the minute and second ?ag (bit msf) is set logic 1 when either the seconds or the minutes counter increments according to the currently enabled interrupt. the ?ag can be read and cleared by the interface. the status of bit msf does not affect the int pulse generation. if the msf ?ag is not cleared prior to the next coming interrupt period, an int pulse will still be generated. the purpose of the ?ag is to allow the controlling system to interrogate the pcf2123 and identify the source of the interrupt, i.e., minute or second, countdown timer or alarm. table 25. register countdown_timer (address 0ah) bits description bit symbol value description reference 7 to 0 countdown_timer[7:0] 0h to ffh countdown period in seconds: where n is the countdown value section 9.8.4 countdownperiod n sourceclockfrequency -------------------------------------------------------------- - = in this example, ti_tp is set to logic 1 resulting in 1 64 hz wide interrupt pulse and the msf ?ag is not cleared after an interrupt. fig 15. int example for mi and si table 26. effect of bits mi and si on int generation minute interrupt (bit mi) second interrupt (bit si) result 0 0 no interrupt generated 1 0 an interrupt once per minute 0 1 an interrupt once per second 1 1 an interrupt once per second 001aaf905 58 59 59 00 11 seconds counter minutes counter int when si enabled msf when si enabled int when only mi enabled msf when only mi enabled 12 00 01
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 21 of 55 nxp semiconductors pcf2123 spi real time clock/calendar the duration of both of these timers will be affected by the register offset_register (see section 9.11 ). only when the offset_register has the value 00h the periods will be consistent. 9.8.4 countdown timer function the 8-bit countdown timer at address 0fh is controlled by the register timer_clkout at address 0eh. the register timer_clkout selects one of 4 source clock frequencies for the timer (4.096 khz, 64 hz, 1 hz, or 1 60 hz) and enables or disables the timer. [1] when not in use, ctd must be set to 1 60 hz for power saving. [2] time periods can be affected by correction pulses. remark: note that all timings which are generated from the 32.768 khz oscillator are based on the assumption that there is 0 ppm deviation. deviation in oscillator frequency will result in deviation in timings. this is not applicable to interface timing. the timer counts down from a software-loaded 8-bit binary value, n. loading the counter with 0 stops the timer. values from 1 to 255 are valid. when the counter reaches 1, the countdown timer ?ag (bit tf) will be set and the counter automatically re-loads and starts the next timer period. reading the timer will return the current value of the countdown counter (see figure 16 ). table 27. effect of mi and si on msf minute interrupt (bit mi) second interrupt (bit si) result 0 0 msf never set 1 0 msf set when minutes counter increments 0 1 msf set when seconds counter increments 1 1 msf set when seconds counter increments table 28. bits ctd0 and ctd1 for timer frequency selection and countdown timer durations ctd[1:0] timer source clock frequency [1] delay minimum timer duration n= 1 maximum timer duration n = 255 00 4.096 khz 244 m s 62.256 ms 01 64 hz 15.625 ms 3.984 s 10 1 hz [2] 1 s 255 s 11 1 60 hz [2] 60 s 4 h 15 min
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 22 of 55 nxp semiconductors pcf2123 spi real time clock/calendar if a new value of n is written before the end of the current timer period, then this value will take immediate effect. nxp does not recommend changing n without ?rst disabling the counter (by setting bit te = 0). the update of n is asynchronous to the timer clock, therefore changing it without setting bit te = 0 may result in a corrupted value loaded into the countdown counter which results in an undetermined countdown period for the ?rst period. the countdown value n will, however, be correctly stored and correctly loaded on subsequent timer periods. when the countdown timer ?ag is set, an interrupt signal on int will be generated provided that this mode is enabled. see section 9.9.2 for details on how the interrupt can be controlled. when starting the timer for the ?rst time, the ?rst period will have an uncertainty which is a result of the enable instruction being generated from the interface clock which is asynchronous from the timer source clock. subsequent timer periods will have no such delay. the amount of delay for the ?rst timer period will depend on the chosen source clock, see t ab le 29 . at the end of every countdown, the timer sets the countdown timer ?ag (bit tf). bit tf may only be cleared by software. the asserted bit tf can be used to generate an interrupt ( int). the interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of bit tf. bit ti_tp is used to control this mode selection and the interrupt output may be disabled with bit tie, see t ab le 6 . in this example it is assumed that the timer ?ag is cleared before the next countdown period expires and that the pin int is set to pulsed mode. fig 16. general countdown timer behavior table 29. first period delay for timer counter value n timer source clock minimum timer period maximum timer period 4.096 khz n n + 1 64 hz n n + 1 1 hz (n - 1) + 1 64 hz n + 1 64 hz 1 60 hz (n - 1) + 1 64 hz n + 1 64 hz 001aaf906 n duration of first timer period after enable may range from n - 1 to n + 1 03 xx 02 01 03 02 01 03 02 01 03 n 03 xx countdown value, n timer source clock countdown counter te tf int
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 23 of 55 nxp semiconductors pcf2123 spi real time clock/calendar when reading the timer, the current countdown value is returned and not the initial value n. since it is not possible to freeze the countdown timer counter during read back, it is recommended to read the register twice and check for consistent results. timer source clock frequency selection of 1 hz and 1 60 hz will be affected by the offset_register. the duration of a program period will vary according to when the offset is initiated. for example, if a 100 s timer is set using the 1 hz clock as source, then some 100 s periods will contain correction pulses and therefor be longer or shorter depending on the setting of the offset_register. see section 9.11 to understand the operation of the offset_register. 9.8.5 timer ?ags when a minute or second interrupt occurs, bit msf is set logic 1. similarly, at the end of a timer countdown or alarm event, bit tf or af are set logic 1. these bits maintain their value until overwritten by software. if both countdown timer and minute or second interrupts are required in the application, the source of the interrupt can be determined by reading these bits. to prevent one ?ag being overwritten while clearing another a logical and is performed during a write access. a ?ag is cleared by writing logic 0 whilst a ?ag is not cleared by writing logic 1. writing logic 1 will result in the ?ag value remaining unchanged. three examples are given for clearing the ?ags. clearing the ?ags is made by a write command, therefore bits 7, 6, 4, 1 and 0 must be written with their previous values. repeatedly re-writing these bits has no in?uence on the functional behavior. t ab le 31 , t ab le 32 and t ab le 33 show what instruction must be sent to clear the appropriate ?ag. clearing the alarm ?ag (bit af) operates in exactly the same way, see section 9.7.5 . table 30. flag location in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 - - msf - af tf - - table 31. example to clear only tf (bit 2) in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 - - 1 - 1 0 - - table 32. example to clear only msf (bit 5) in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 - - 0 - 1 1 - - table 33. example to clear both tf and msf (bit 2 and bit 5) in register control_2 register bit 7 6 5 4 3 2 1 0 control_2 - - 0 - 1 0 - -
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 24 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.9 interrupt output an active low interrupt signal is available at pin int. operation is controlled via the bits of register control_2. interrupts may be sourced from four places: second and minute timer, countdown timer, alarm function or offset function. with bit ti_tp, the timer generated interrupts can be con?gured to either generate a pulse or to follow the status of the interrupt ?ags (bits tf and msf). correction interrupt pulses are always 1 128 second long. alarm interrupts always follow the condition of af. remark: note that the interrupts from the four sources are wired-or, meaning they will mask one another (see figure 17 ). 9.9.1 minute and second interrupts the pulse generator for the minute and second interrupt operates from an internal 64 hz clock and consequently generates a pulse of 1 64 second in duration. when bits si, mi, tie, aie and cie are all disabled, pin int will remain high-impedance. fig 17. interrupt scheme 001aai555 seconds counter si 0 1 msf: minute second flag clear set pulse generator 1 clear trigger te si mi minutes counter countdown counter mi from interface: clear msf to interface: read msf af: alarm flag clear set to interface: read af 0 1 tf: timer clear set pulse generator 2 clear trigger tie int from interface: clear tf from interface: clear af set alarm flag, af offset circuit: add/substract 1/64 hz pulse to interface: read tf ti_tp aie e.g.aie pulse generator 3 clear trigger cie from interface: set cie 0 1
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 25 of 55 nxp semiconductors pcf2123 spi real time clock/calendar if the msf ?ag is cleared before the end of the int pulse, then the int pulse is shortened. this allows the source of a system interrupt to be cleared immediately it is serviced, i.e., the system does not have to wait for the completion of the pulse before continuing; see figure 18 . instructions for clearing msf are given in section 9.8.5 . the timing shown for clearing bit msf in figure 18 is also valid for the non-pulsed interrupt mode i.e. when bit ti_tp = 0, int may be shortened by setting both mi and si or msf to logic 0. 9.9.2 countdown timer interrupts the generation of interrupts from the countdown timer is controlled via bit tie. the pulse generator for the countdown timer interrupt also uses an internal clock, but this time it is dependent on the selected source clock for the countdown timer and on the countdown value n. as a consequence, the width of the interrupt pulse varies (see t ab le 34 ). [1] n = loaded countdown value. timer stopped when n = 0. if the tf ?ag is cleared before the end of the int pulse, then the int pulse is shortened. this allows the source of a system interrupt to be cleared immediately it is serviced, i.e., the system does not have to wait for the completion of the pulse before continuing (see figure 19 ). instructions for clearing msf can be found in section 9.8.5 . (1) indicates normal duration of int pulse (bit ti_tp = 1) fig 18. example of shortening the int pulse by clearing the msf ?ag 001aaf908 58 seconds counter msf int scl instruction 59 clear instruction 8th clock (1) table 34. int operation (bit ti_tp = 1) source clock (hz) int period (s) n = 1 [1] n > 1 4096 1 8192 1 4096 64 1 128 1 64 1 1 64 1 64 1 60 1 64 1 64
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 26 of 55 nxp semiconductors pcf2123 spi real time clock/calendar the timing shown for clearing bit tf in figure 19 is also valid for the non-pulsed interrupt mode, i.e., when bit ti_tp = 0; int may be shortened by setting bit tie to logic 0. 9.9.3 alarm interrupts the generation of interrupts from the alarm function is controlled via bit aie (see t ab le 6 ). if bit aie is enabled, the int pin follows the condition of bit af. clearing bit af will immediately clear int. no pulse generation is possible for alarm interrupts (see figure 20 ). 9.9.3.1 correction pulse interrupts interrupt pulses generated by correction events can be shortened by writing logic 1 to bit cie in register control_1. (1) indicates normal duration of int pulse (bit ti_tp = 1). fig 19. example of shortening the int pulse by clearing the tf ?ag 001aaf909 01 countdown counter cdtf int scl instruction n clear instruction 8th clock (1) example where only the minute alarm is used and no other interrupts are enabled. fig 20. af timing 001aaf910 44 45 minute counter minute alarm af int scl instruction 45 clear instruction 8th clock
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 27 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.10 clock output a programmable square wave is available at pin clkout. operation is controlled by the cof[2:0] bits in the register timer_clkout. frequencies of 32.768 khz (default) down to 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. pin clkout is an open-drain output and enabled at power-on. when disabled the output is high-impedance. the duty cycle of the selected clock is not controlled. however, due to the nature of the clock generation, all will be 50 : 50 except the 32.768 khz frequencies. the stop bit function can also affect the clkout signal, depending on the selected frequency. when the stop bit is set to logic 1, the clkout pin will generate a continuous low for those frequencies that can be stopped. for more details of the stop bit function see section 9.13 . [1] duty cycle de?nition: % high-level time : % low-level time. [2] 1 hz clock pulses will be affected by offset correction pulses. 9.10.1 clkoe pin the clkoe pin can be used to block the clkout function and force the clkout pin to an high-impedance state. the effect is the same as setting cof[2:0] = 111. 9.11 offset register the pcf2123 incorporates an offset register (address 0dh) which can be used to implement several functions, such as: ? ageing adjustment ? temperature compensation ? accuracy tuning the offset is made once every two hours in the normal mode, or once every hour in the course mode. each lsb will introduce an offset of 2.17 ppm for normal mode and 4.34 ppm for course mode. the values of 2.17 ppm and 4.34 ppm are based on a nominal 32.768 khz clock. the offset value is coded in twos complement giving a range of +63 lsb to - 64 lsb. table 35. clkout frequency selection bits cof[2:0] clkout frequency (hz) typical duty cycle [1] effect of stop bit 000 32768 60 : 40 to 40 : 60 no effect 001 16384 50 : 50 no effect 010 8192 50 : 50 no effect 011 4096 50 : 50 clkout = low 100 2048 50 : 50 clkout = low 101 1024 50 : 50 clkout = low 110 1 [2] 50 : 50 clkout = low 111 clkout = high-z - -
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 28 of 55 nxp semiconductors pcf2123 spi real time clock/calendar [1] default mode. the correction is made by adding or subtracting 64 hz clock correction pulses, thereby changing the period of a single second. in normal mode, the correction is triggered once per two hours and then correction pulses are applied once per minute until the programmed correction values has been implement. in course mode, the correction is triggered once per hour and then correction pulses are applied once per minute up to a maximum of 60 minutes. when correction values greater than 60 are used, additional correction pulses are made in the 59th minute (see t ab le 38 ). table 36. register offset_register offset[6:0] offset value in decimal offset value in ppm normal mode mode = 0 course mode mode = 1 0 1 1 1 1 1 1 +63 +136.71 +273.42 0 1 1 1 1 1 0 +62 +134.54 +269.08 :::: 0 0 0 0 0 1 0 +2 +4.34 +8.68 0 0 0 0 0 0 1 +1 +2.17 +4.34 0000000 0 [1] 00 1111111 - 1 - 2.17 - 4.34 1111110 - 2 - 4.34 - 8.68 :::: 1000001 - 63 - 136.71 - 273.42 1000000 - 64 - 138.88 - 277.76 table 37. example of converting the offset in ppm to seconds offset in ppm seconds per day week month year 2.17 0.187 1.31 5.69 68.2 4.34 0.375 2.62 11.4 136
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 29 of 55 nxp semiconductors pcf2123 spi real time clock/calendar [1] example is given in a time range from 2:00 to 2:59. [2] correction int pulses are 1 128 s wide. for multiple pulses they are repeated at 1 64 s interval. it is possible to monitor when correction pulses are applied. the correction interrupt enable mode (bit cie) will generate a 1 128 second pulse on int for every correction applied. in the case where multiple correction pulses are applied, a 1 128 second interrupt pulse will be generated and repeated every 1 64 seconds. correction is applied to the 1 hz clock. any timer or clock output using a frequency of 1 hz or below will also be affected by the correction pulses. table 38. correction pulses for course mode correction value hour:minute [1] correction pulses on int per minute [2] +1 or - 1 02:00 1 02:01 to 02:59 0 +2 or - 2 02:00 1 02:01 1 02:02 to 02:59 0 +3 or - 3 02:00 1 02:01 1 02:02 1 02:03 to 02:59 0 ::: +59 or - 59 02:00 to 02:58 1 02:59 0 +60 or - 60 02:00 to 02:59 1 +61 or - 61 02:00 to 02:58 1 02:59 2 +62 or - 62 02:00 to 02:58 1 02:59 3 +63 or - 63 02:00 to 02:58 1 02:59 4 - 64 02:00 to 02:58 1 02:59 5
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 30 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 9.12 external clock test mode a test mode is available which allows for on-board testing. in this mode it is possible to set up test conditions and control the operation of the rtc. the test mode is entered by setting bit ext_test in register control_1. then pin clkout becomes an input. the test mode replaces the internal clock signal with the signal applied to pin clkout. the signal applied to pin clkout should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. the internal clock, now sourced from clkout, is divided down to 1 hz by a 2 6 divide chain called a prescaler. the prescaler can be set into a known state by using bit stop. when bit stop is set, the prescaler is reset to 0. (stop must be cleared before the prescaler can operate again.) from a stop condition, the ?rst 1 second increment will take place after 32 positive edges on pin clkout. thereafter, every 64 positive edges will cause a 1 second increment. remark: entry into test mode is not synchronized to the internal 64 hz clock. when entering the test mode, no assumption as to the state of the prescaler can be made. operation example: 1. set ext_test test mode (register control_1, bit ext_test = 1). 2. set stop (control_1, bit stop = 1). 3. clear stop (control_1, bit stop = 0). 4. set time registers to desired value. 5. apply 32 clock pulses to pin clkout. 6. read time registers to see the ?rst change. table 39. effect of correction pulses frequency (hz) effect of correction clkout 32768 no effect 16384 no effect 8192 no effect 4096 no effect 2048 no effect 1024 no effect 1 effected time source clock 4096 no effect 64 no effect 1 effected 1 60 effected
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 31 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 7. apply 64 clock pulses to pin clkout. 8. read time registers to see the second change. repeat 7 and 8 for additional increments. 9.13 stop bit function the function of the stop bit is to allow for accurate starting of the time circuits. the stop bit function will cause the upper part of the prescaler (f 2 to f 14 ) to be held in reset and thus no 1 hz ticks will be generated. the time circuits can then be set and will not increment until the stop bit is released (see figure 22 and t ab le 40 ). the stop bit function will not affect the output of 32.768 khz, 16.384 khz or 8.192 khz (see section 9.10 ). the lower two stages of the prescaler (f 0 and f 1 ) are not reset and because the spi-bus is asynchronous to the crystal oscillator, the accuracy of re-starting the time circuits will be between 0 and one 8.192 khz cycle (see figure 22 ). the ?rst increment of the time circuits is between 0.499888 s and 0.500000 s after stop bit is released. the uncertainty is caused by the prescaler bits f 0 and f 1 not being reset (see t ab le 40 ). fig 21. stop bit functional diagram 001aai556 oscillator 32768 hz 16384 hz oscillator stop detector f 0 f 1 f 13 reset f 14 reset f 2 reset 2 hz 1 hz 1024 hz 16384 hz 8192 hz 1 hz tick stop clkout source oscillator stop flag 8192 hz 4096 hz fig 22. stop bit release timing 001aaf912 8192 hz stop released 0 m s to 122 m s
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 32 of 55 nxp semiconductors pcf2123 spi real time clock/calendar [1] f 0 is clocked at 32.768 khz. 9.14 3-line serial interface data transfer to and from the device is made via a 3-wire spi-bus (see t ab le 41 ). the data lines for input and output are split. the data input and output lines can be connected together to facilitate a bidirectional data bus. the chip enable signal is used to identify the transmitted data. each data transfer is a byte, with the most signi?cant bit (msb) sent ?rst (see figure 24 ). table 40. first increment of time circuits after stop bit release bit prescaler bits [1] 1 hz tick time comment stop f 0 f 1 -f 2 to f 14 hh:mm:ss clock is running normally 0 01-0 0001 1101 0100 12:45:12 prescaler counting normally stop bit is activated by user. f 0 f 1 are not reset and values cannot be predicted externally 1 xx-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen new time is set by user 1 xx-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen stop bit is released by user 0 xx-0 0000 0000 0000 08:00:00 prescaler is now running xx-1 0000 0000 0000 08:00:00 - xx-0 1000 0000 0000 08:00:00 - xx-1 1000 0000 0000 08:00:00 - : :: 11-1 1111 1111 1110 08:00:00 - 00-0 0000 0000 0001 08:00:01 0 to 1 transition of f 14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : :: 11-1 1111 1111 1111 08:00:01 - 00-0 0000 0000 0000 08:00:01 - 10-0 0000 0000 0000 08:00:01 - : :: 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0001 08:00:02 0 to 1 transition of f 14 increments the time circuits 001aaf913 0.499888 - 0.500000 s 1 s
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 33 of 55 nxp semiconductors pcf2123 spi real time clock/calendar the transmission is controlled by the active high chip enable signal ce. the ?rst byte transmitted is the command byte. subsequent bytes will be either data to be written or data to be read. data is sampled on the rising edge of the clock and transferred internally on the falling edge. the command byte de?nes the address of the ?rst register to be accessed and the read/write mode. the address counter will auto increment after every access and will rollover to zero after the last register is accessed. the read/ wr ite bit (r/ w) de?nes if the following bytes will be read or write information. in figure 25 , the register seconds is set to 45 seconds and the register minutes is set to 10 minutes. table 41. serial interface symbol function description ce chip enable input when low, the interface is reset; pull-down resistor included; active input may be higher than v dd , but may not be wired permanently high scl serial clock input when ce is low, this input may ?oat; input may be higher than v dd sdi serial data input when ce is low, input may ?oat; input may be higher than v dd ; input data is sampled on the rising edge of scl sdo serial data output push-pull output; drives from v ss to v dd ; output data is changed on the falling edge of scl; will be high-z when not driving; may be connected directly to sdi fig 23. sdi, sdo con?gurations fig 24. data transfer overview table 42. command byte de?nition bit symbol value description 7r/ w data read or data write selection 0 write data 1 read data 6 to 4 sa 001 subaddress; other codes will cause the device to ignore data transfer 3 to 0 ra 0h to fh register address range 001aai560 sdi two wire mode sdo sdi single wire mode sdo 001aaf914 command data bus chip enable data data data
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 34 of 55 nxp semiconductors pcf2123 spi real time clock/calendar in figure 26 , the months and years registers are read. in this example, pins sdi and sdo are not connected together. for this con?guration, it is important that pin sdi is never left ?oating. it must always be driven either high or low. if pin sdi is left open, high i dd currents may result. short transition periods in the order of 200 ns will not cause any problems. 9.14.1 interface watchdog timer during read/write operations, the time counting circuits are frozen. to prevent a situation where the accessing device becomes locked and does not clear the interface by setting pin ce low, the pcf2123 has a built in watchdog timer. should the interface be active for more than 1 s from the time a valid subaddress is transmitted, then the pcf2123 will automatically clear the interface and allow the time counting circuits to continue counting. ce must return low once more before a new data transfer can be executed. fig 25. serial bus write example 001aaf915 xx address counter ce sdi scl 02 03 04 seconds data 45 bcd minutes data 10 bcd r/w addr 02 hex b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 1 b0 0 b7 0 b6 1 b5 0 b4 0 b3 0 b2 1 b1 0 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 0 fig 26. serial bus read example 001aaf916 xx address counter ce sdo sdi scl 07 08 09 months data 11 bcd years data 06 bcd r/w addr 07 hex b7 1 b6 0 b5 0 b4 1 b3 0 b2 1 b1 1 b0 1 b7 0 b6 0 b5 0 b4 1 b3 0 b2 0 b1 0 b0 1 b7 0 b6 0 b5 0 b4 0 b3 0 b2 1 b1 1 b0 0
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 35 of 55 nxp semiconductors pcf2123 spi real time clock/calendar the watchdog is implemented to prevent the excessive loss of time due to interface access failure e.g. if main power is removed from a battery backed-up system during an interface access. each time the watchdog period is exceeded, 1 s will be lost from the time counters. the watchdog will trigger between 1 s and 2 s after receiving a valid subaddress. a. correct data transfer: read or write b. incorrect data transfer; read or write fig 27. interface watchdog timer 001aai563 valid sub-address running time counters wd timer data ce wd timer running time counters frozen running data t w(ce) < 1 s data data 001aai564 valid sub-address running time counters wd timer data ce wd timer running data transfer fail wd trips time counters frozen running data 1 s < t w(ce) < 2 s data data
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 36 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 10. limiting values [1] with respect to v ss . [2] pass level; human body model (hbm) according to ref . 7 jesd22-a114 [3] pass level; machine model (mm), according to ref . 8 jesd22-a115 [4] pass level; latch-up testing, according to ref . 9 jesd78 at maximum ambient temperature (t amb(max) = +85 c). [5] according to the nxp store and transport requirements (see ref . 11 nx3-00092 ) the devices have to be stored at a temperature of +8 cto+45 c and a humidity of 25 % to 75 %. for long term storage products deviant conditions are described in that document. table 43. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage [1] - 0.5 +6.5 v i dd supply current - 50 +50 ma v i input voltage [1] - 0.5 +6.5 v v o output voltage [1] - 0.5 +6.5 v i i input current - 10 +10 ma i o output current - 10 +10 ma p tot total power dissipation - 300 mw t amb ambient temperature - 40 +85 c v esd electrostatic discharge voltage hbm [2] - 3000 v mm [3] - 300 v i lu latch-up current [4] - 200 ma t stg storage temperature [5] - 65 +150 c
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 37 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 11. static characteristics table 44. static characteristics v dd = 1.1 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; f osc = 32.768 khz; quartz r s =15k w ; c l = 7 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dd supply voltage for clock data integrity; spi-bus inactive [1] 1.1 - 5.5 v t amb =25 c - 0.9 - v spi-bus active 1.6 - 5.5 v i dd supply current spi-bus active f scl = 4.5 mhz; v dd =5v - 250 400 m a f scl = 1.0 mhz; v dd =3v -3080 m a spi-bus inactive; clkout disabled [2] t amb =25 c; v dd = 2.0 v - 100 - na t amb =25 c; v dd = 3.0 v - 110 - na t amb =25 c; v dd = 5.0 v - 120 - na spi-bus inactive; clkout disabled; t amb = - 40 c to +85 c [2] v dd = 2.0 v - - 330 na v dd = 3.0 v - - 350 na v dd = 5.0 v - - 380 na spi-bus inactive; clkout enabled at 32 khz; t amb =25 c v dd = 2.0 v - 260 - na v dd = 3.0 v - 340 - na v dd = 5.0 v - 520 - na spi-bus inactive; clkout enabled at 32 khz; t amb = - 40 c to +85 c v dd = 2.0 v - - 450 na v dd = 3.0 v - - 550 na v dd = 5.0 v - - 750 na inputs v il low-level input voltage - - 0.3v dd v v ih high-level input voltage 0.7v dd --v v i input voltage on pins ce, sdi, scl, osci, clkoe, clkout - 0.5 - +5.5 v
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 38 of 55 nxp semiconductors pcf2123 spi real time clock/calendar [1] for reliable oscillator start at power-on: v dd =v dd(min) + 0.3 v. [2] timer source clock = 1 60 hz, level of pins ce, sdi and scl is v dd or v ss . [3] implicit by design. [4] refers to external pull-up voltage. [5] integrated load capacitance, c l(itg) , is a calculation of c osci and c osco in series. i l leakage current v i =v dd or v ss on pins sdi, scl, osci, clkoe, clkout - 10 +1 m a v i =v ss on pin ce - 10 - m a r pd pull-down resistance on pin ce - 240 550 k w c i input capacitance on pins sdi, scl, clkoe and ce [3] --7pf outputs v o output voltage on pins clkout and int [4] - 0.5 - +5.5 v on pin osco - 0.5 - +5.5 v on pin sdo - 0.5 - v dd + 0.5 v v oh high-level output voltage on pin sdo 0.8v dd -v dd v v ol low-level output voltage on pin sdo v ss - 0.2v dd v on pins clkout and int; v dd =5v; i ol = 1.5 ma v ss - 0.4 v i oh high-level output current output source current; v oh = 4.6 v; v dd = 5 v on pin sdo 1.5 - - ma i ol low-level output current output sink current; v ol = 0.4 v; v dd = 5 v on pins int, sdo and clkout 1.5 - - ma i lo output leakage current v o =v dd or v ss - 10 +1 m a c l(itg) integrated load capacitance on pins osco and osci [5] 3.3 7 14 pf r s series resistance - - 100 k w table 44. static characteristics continued v dd = 1.1 v to 5.5 v; v ss =0v; t amb = - 40 c to +85 c; f osc = 32.768 khz; quartz r s =15k w ; c l = 7 pf; unless otherwise speci?ed. symbol parameter conditions min typ max unit c litg () c osci c osco () c osci c osco + () -------------------------------------------- =
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 39 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 12. dynamic characteristics table 45. spi-bus characteristics v ss =0v;t amb = - 40 c to +85 c. all timing values are valid within the operating supply voltage and temperature range and referenced to v il and v ih with an input voltage swing of v ss to v dd . symbol parameter conditions v dd = 1.6 v v dd = 2.4 v v dd = 3.3 v v dd = 5.0 v unit min max min max min max min max timing characteristics (see figure 28 ) f clk(scl) scl clock frequency - 2.9 - 4.54 - 5.71 - 8.0 mhz t scl scl time 345 - 220 - 175 - 125 - ns t clk(h) clock high time 90 - 50 - 45 - 40 - ns t clk(l) clock low time 200 - 120 - 95 - 70 - ns t r rise time for scl signal - 100 - 100 - 50 - 50 ns t f fall time for scl signal - 100 - 100 - 50 - 50 ns t su(ce) ce set-up time 40 - 35 - 30 - 25 - ns t h(ce) ce hold time 40 - 30 - 25 - 15 - ns t rec(ce) ce recovery time 30 - 25 - 20 - 15 - ns t w(ce) ce pulse width measured after valid subaddress is received - 0.99 - 0.99 - 0.99 - 0.99 s t su set-up time set-up time for sdi data 10-5-3-2-ns t h hold time hold time for sdi data 25 - 10 - 8 - 5 - ns t d(r)sdo sdo read delay time bus load = 50 pf - 190 - 108 - 85 - 60 ns t dis(sdo) sdo disable time no load value; bus will be held up by bus capacitance; use rc time constant with application values - 70 - 45 - 40 - 27 ns t t(sdi-sdo) transition time from sdi to sdo to avoid bus con?ict 0 - 0 - 0 - 0 - ns
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 40 of 55 nxp semiconductors pcf2123 spi real time clock/calendar fig 28. spi-bus timing 001aai554 r/w sa2 ra0 b7 b6 b0 b7 b6 b0 b0 b6 b7 sdi sdo sdo hi z hi z sdi scl ce write read t w(ce) 80% 20% t clk(l) t f t h(ce) t rec(ce) t dis(sdo) t d(r)sdo t t(sdi-sdo) t r t h t su t clk(h) t scl t su(ce)
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 41 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 13. application information a 1 farad super capacitor combined with a low v f diode can be used as a standby or back-up supply. with the rtc in its minimum power con?guration i.e. timer off and clkout off, the rtc may operate for weeks. fig 29. typical application diagram 001aai557 clkoe v dd clkout v ss osci osco ce scl sdi sdo pcf2123 int 100 nf 1 f supercapacitor
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 42 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 14. package outline fig 30. package outline sot402-1 (tssop14) of pcf2123ts unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 43 of 55 nxp semiconductors pcf2123 spi real time clock/calendar fig 31. package outline sot758-1 (hvqfn16) of pcf2123bs terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.75 1.45 y 1 3.1 2.9 1.75 1.45 e 1 1.5 e 2 1.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot758-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot758-1 hvqfn16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 3 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 58 16 13 12 9 4 1 x d e c b a e 2 02-03-25 02-10-21 terminal 1 index area 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 44 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 15. bare die outline fig 32. bare die outline of pcf2123u/10 references outline version european projection issue date iec jedec jeita pcf2123u/10 wire bond die; 12 bonding pads; 1.492 x 1.449 x 0.20 mm pcf2123u/10 08-07-16 08-07-24 unit mm nom 0.20 1.492 1.296 0.09 0.081 0.09 a dimensions (mm are the original dimensions) d (1) e (1) 1.449 e d p 1 (2) p 2 (3) p 3 (2) p 4 (3) 0.081 0 scale 1 mm a notes 1. dimension includes saw lane 2. p 1 and p 3 : pad size 3. p 2 and p 4 : passivation opening p 4 p 3 p 2 p 1 detail x d e e d x y 0 0 12 11 10 9 8 7 6 5 4 3 2 1 x table 46. bonding pad locations all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see figure 32 . symbol pad coordinates x y sdo 1 648.0 - 575.0 sdi 2 648.0 - 377.0 scl 3 648.0 - 179.0 clkoe 4 648.0 171.2 clkout 5 648.0 369.2 v dd 6 648.0 625.7 osci 7 - 648.0 639.0 osco 8 - 648.0 421.9 test 9 - 648.0 - 25.9 int 10 - 648.0 - 223.9 ce 11 - 648.0 - 441.0 v ss 12 - 648.0 - 639.0
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 45 of 55 nxp semiconductors pcf2123 spi real time clock/calendar fig 33. bare die outline of pcf2123u/12 references outline version european projection issue date iec jedec jeita pcf2123u/12 - - - - - - - - - pcf2123u_12_do 09-10-17 09-10-19 unit mm max nom min 0.22 0.018 0.015 0.012 1.492 1.449 1.296 0.198 0.09 0.09 0.084 0.081 0.078 a dimensions note 1. dimension includes saw lane. 2. p 1 and p 3 : pad size. 3. p 2 and p 4 : bump size. wlcsp12: wafer level chip size package; 12 bumps; 1.492 x 1.449 x 0.22 mm pcf2123u/12 a 1 a 2 0.2 d (1) e (1) ep 1 (2) p 2 (3) 0.084 0.081 0.078 p 3 (2) p 4 (3) 0 0.5 1 mm scale x detail y p 2 p 1 p 4 p 3 detail x a 1 a 2 a y 0 x 0 y d e e e pc2123-1 7 8 9 10 11 12 6 5 4 3 2 1
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 46 of 55 nxp semiconductors pcf2123 spi real time clock/calendar [1] the x/y coordinates of the alignment mark location represent the position of the ref point (see figure 34 ) with respect to the center (x/y = 0) of the chip; see figure 32 and figure 33 . [2] the x/y values of the dimensions represent the extensions of the alignment mark in direction of the coordinate axis (see figure 34 ). table 47. bump locations all x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip; see figure 33 . symbol bump coordinates x y sdo 1 648.0 - 575.0 sdi 2 648.0 - 377.0 scl 3 648.0 - 179.0 clkoe 4 648.0 171.2 clkout 5 648.0 369.2 v dd 6 648.0 625.7 osci 7 - 648.0 639.0 osco 8 - 648.0 421.9 test 9 - 648.0 - 25.9 int 10 - 648.0 - 223.9 ce 11 - 648.0 - 441.0 v ss 12 - 648.0 - 639.0 table 48. alignment mark dimension and location coordinates x y location [1] 693 - 516.2 dimension 16 m m13 m m fig 34. alignment mark 013aaa231 ref y x
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 47 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 16. handling information all input and output pins are protected against electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards.
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 48 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 17. packing information (1) die marking code. seal ring plus gap to active circuit ~18 m m. wafer thickness 200 m m. pcf2123u/10: bad die are inked off. pcf2123u/12: bad die are marked in wafer mapping. fig 35. pcf2123u/10 and pcf2123u/12 sawn wafer on ?lm frame carrier 013aaa232 saw lane ~18 m m 45 m m 70 m m ~18 m m detail x 1.449 mm 1.492 mm 1 1 1 1 x straight edge of the wafer 1.2 +0 mm - 0.1 73.68 mm 71.79 mm ? 193.50 mm ? 225.50 mm 214.50 mm 214.50 mm 0.25 metal frame plastic film (1)
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 49 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 50 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 18.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 36 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 49 and 50 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 36 . table 49. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 50. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 51 of 55 nxp semiconductors pcf2123 spi real time clock/calendar for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 19. abbreviations msl: moisture sensitivity level fig 36. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 51. abbreviations acronym description cmos complementary metal oxide semiconductor bcd binary coded decimal ffc film frame carrier hbm human body model lsb least signi?cant bit mm machine model mos metal oxide semiconductor msb most signi?cant bit msl moisture sensitivity level pcb printed-circuit board rtc real time clock smd surface mount device spi serial peripheral interface
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 52 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 20. references [1] an10365 surface mount re?ow soldering description [2] an10706 handling bare die [3] an10853 handling precautions of esd sensitive devices [4] iec 60134 rating systems for electronic tubes and valves and analogous semiconductor devices [5] iec 61340-5 protection of electronic devices from electrostatic phenomena [6] ipc/jedec j-std-020d moisture/re?ow sensitivity classi?cation for nonhermetic solid state surface mount devices [7] jesd22-a114 electrostatic discharge (esd) sensitivity testing human body model (hbm) [8] jesd22-a115 electrostatic discharge (esd) sensitivity testing machine model (mm) [9] jesd78 ic latch-up test [10] jesd625-a requirements for handling electrostatic-discharge-sensitive (esds) devices [11] nx3-00092 nxp store and transport requirements [12] snv-fa-01-02 marking formats integrated circuits
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 53 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 21. revision history table 52. revision history document id release date data sheet status change notice supersedes pcf2123_2 20091204 product data sheet - pcf2123_1 modi?cations: ? added product type pcf2123u/12 pcf2123_1 20081119 product data sheet - -
pcf2123_2 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 02 4 december 2009 54 of 55 nxp semiconductors pcf2123 spi real time clock/calendar 22. legal information 22.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 22.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 22.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. bare die all die are tested on compliance with their related technical speci?cations as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the nxp semiconductors storage and transportation conditions. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post-packing tests performed on individual die or wafers. nxp semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, nxp semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used. all die sales are conditioned upon and subject to the customer entering into a written die sale agreement with nxp semiconductors through its legal department. 22.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 23. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors pcf2123 spi real time clock/calendar ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 4 december 2009 document identifier: pcf2123_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 device protection diagram . . . . . . . . . . . . . . . . 5 9 functional description . . . . . . . . . . . . . . . . . . . 6 9.1 low power operation. . . . . . . . . . . . . . . . . . . . . 6 9.1.1 power consumption with respect to quartz series resistance . . . . . . . . . . . . . . . . . . 6 9.1.2 power consumptions with respect to timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9.2 register overview . . . . . . . . . . . . . . . . . . . . . . . 8 9.3 control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 9.3.1 register control_1 . . . . . . . . . . . . . . . . . . . . . . 9 9.3.2 register control_2 . . . . . . . . . . . . . . . . . . . . . 10 9.4 os ?ag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 9.5 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9.6 time and date function . . . . . . . . . . . . . . . . . . 13 9.6.1 register seconds . . . . . . . . . . . . . . . . . . . . . . 13 9.6.2 register minutes. . . . . . . . . . . . . . . . . . . . . . . 13 9.6.3 register hours . . . . . . . . . . . . . . . . . . . . . . . . 13 9.6.4 register days . . . . . . . . . . . . . . . . . . . . . . . . . 14 9.6.5 register weekdays. . . . . . . . . . . . . . . . . . . . . 14 9.6.6 register months . . . . . . . . . . . . . . . . . . . . . . . 14 9.6.7 register years . . . . . . . . . . . . . . . . . . . . . . . . 15 9.6.8 setting and reading the time. . . . . . . . . . . . . . 15 9.7 alarm function. . . . . . . . . . . . . . . . . . . . . . . . . 16 9.7.1 register minute_alarm . . . . . . . . . . . . . . . . . . 16 9.7.2 register hour_alarm . . . . . . . . . . . . . . . . . . . 17 9.7.3 register day_alarm . . . . . . . . . . . . . . . . . . . . 17 9.7.4 register weekday_alarm . . . . . . . . . . . . . . . . 17 9.7.5 alarm ?ag . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.8 timer functions . . . . . . . . . . . . . . . . . . . . . . . . 19 9.8.1 register timer_clkout. . . . . . . . . . . . . . . . . . . 19 9.8.2 register countdown_timer . . . . . . . . . . . . . . . 20 9.8.3 minute and second interrupt . . . . . . . . . . . . . . 20 9.8.4 countdown timer function . . . . . . . . . . . . . . . . 21 9.8.5 timer ?ags . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.9 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 24 9.9.1 minute and second interrupts . . . . . . . . . . . . . 24 9.9.2 countdown timer interrupts. . . . . . . . . . . . . . . 25 9.9.3 alarm interrupts . . . . . . . . . . . . . . . . . . . . . . . 26 9.9.3.1 correction pulse interrupts . . . . . . . . . . . . . . . 26 9.10 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.10.1 clkoe pin . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.11 offset register. . . . . . . . . . . . . . . . . . . . . . . . . 27 9.12 external clock test mode . . . . . . . . . . . . . . . . 30 9.13 stop bit function . . . . . . . . . . . . . . . . . . . . . . 31 9.14 3-line serial interface . . . . . . . . . . . . . . . . . . . 32 9.14.1 interface watchdog timer . . . . . . . . . . . . . . . . 34 10 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 36 11 static characteristics . . . . . . . . . . . . . . . . . . . 37 12 dynamic characteristics . . . . . . . . . . . . . . . . . 39 13 application information . . . . . . . . . . . . . . . . . 41 14 package outline . . . . . . . . . . . . . . . . . . . . . . . . 42 15 bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 44 16 handling information . . . . . . . . . . . . . . . . . . . 47 17 packing information . . . . . . . . . . . . . . . . . . . . 48 18 soldering of smd packages . . . . . . . . . . . . . . 49 18.1 introduction to soldering. . . . . . . . . . . . . . . . . 49 18.2 wave and re?ow soldering . . . . . . . . . . . . . . . 49 18.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 49 18.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 50 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 51 20 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 21 revision history . . . . . . . . . . . . . . . . . . . . . . . 53 22 legal information . . . . . . . . . . . . . . . . . . . . . . 54 22.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 54 22.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 22.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 54 22.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 54 23 contact information . . . . . . . . . . . . . . . . . . . . 54 24 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

▲Up To Search▲

Price & Availability of PCF2123U12AA

	To Download PCF2123U12AA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .